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d a t a sh eet product speci?cation supersedes data of 1997 aug 21 file under integrated circuits, ic02 1998 nov 03 integrated circuits tda8761a 9-bit analog-to-digital converter for digital video
1998 nov 03 2 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a features 9-bit resolution sampling rate up to 40 mhz dc sampling allowed one clock cycle conversion only high signal-to-noise ratio over a large analog input frequency range (8.2 effective bits at 10 mhz full-scale input at f clk = 30 mhz) no missing codes guaranteed in range (ir) cmos output levels ttl and cmos compatible digital inputs 3 to 5 v cmos digital outputs low-level ac clock input signal allowed external reference voltage regulator power dissipation only 158 mw (typical) low analog input capacitance, no buffer amplifier required no sample-and-hold circuit required. applications analog-to-digital conversion for: video data digitizing digital video broadcasting (dvb) cable tv. general description the tda8761a is a 9-bit analog-to-digital converter (adc) for professional video and digital video set box applications. it converts the analog input signal into 9-bit binary-coded digital words at a maximum sampling rate of 40 mhz. its linearity performance ensures the required conversion accuracy in the event of 256-qam demodulator concept and for all symbol frequencies. all digital inputs and outputs are ttl and cmos compatible, although a low-level sine wave clock input signal is allowed. quick reference data note 1. f i = 10 mhz and f clk = 30 mhz; f i = 8 mhz and f clk = 20 mhz. symbol parameter conditions min. typ. max. unit v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output stages supply voltage 3.0 3.3 5.25 v i cca analog supply current - 18 24 ma i ccd digital supply current - 13 18 ma i cco output stages supply current f clk = 30 mhz; ramp input - 12ma inl integral non-linearity f clk = 30 mhz; ramp input - 0.8 1.6 lsb ainl ac integral non-linearity full-scale input sine wave; note 1 - 0.75 0.9 lsb 50% full-scale input sine wave; note 1 - 0.5 0.75 lsb dnl differential non-linearity f clk = 30 mhz; ramp input - 0.3 0.7 lsb adnl ac differential non-linearity full-scale input sine wave; note 1 - 0.5 0.75 lsb 50% full-scale input sine wave; note 1 - 0.3 0.5 lsb f clk(max) maximum clock frequency 40 -- mhz p tot total power dissipation - 158 173 mw
1998 nov 03 3 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a ordering information block diagram type number package name description version TDA8761AM ssop28 plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 fig.1 block diagram. handbook, full pagewidth 12 dgnd2 6 8 7 r lad 9 v rb v rm v rt v i 11 v ccd2 3 26 v cca 21 22 23 24 20 d3 d4 d5 d6 d7 19 18 25 2 d2 d1 17 d0 d8 in range latch cmos outputs latches analog -to - digital converter clock driver mbg910 cmos output 1 clk 10 oe tc tda8761a 13 v cco 4 agnd analog ground digital grounds 27 dgnd1 14 ognd output ground analog voltage input data outputs lsb msb 28 v ccd1 ir output
1998 nov 03 4 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a pinning symbol pin description clk 1 clock input tc 2 twos complement input (active low) v cca 3 analog supply voltage (5 v) agnd 4 analog ground n.c. 5 not connected v rb 6 reference voltage bottom input v rm 7 reference voltage middle v i 8 analog input voltage v rt 9 reference voltage top input oe 10 output enable input (cmos level input, active low) v ccd2 11 digital supply voltage 2 (5 v) dgnd2 12 digital ground 2 v cco 13 supply voltage for output stages (3 to 5 v) ognd 14 output ground n.c. 15 not connected n.c. 16 not connected d0 17 data output; bit 0 (lsb) d1 18 data output; bit 1 d2 19 data output; bit 2 d3 20 data output; bit 3 d4 21 data output; bit 4 d5 22 data output; bit 5 d6 23 data output; bit 6 d7 24 data output; bit 7 d8 25 data output; bit 8 (msb) ir 26 in range data output dgnd1 27 digital ground 1 v ccd1 28 digital supply voltage 1 (5 v) fig.2 pin configuration. handbook, halfpage 1 2 3 4 5 6 7 8 9 10 11 12 13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 clk tc cca agnd n.c. rb rm i rt oe ccd2 dgnd2 cco ognd ccd1 dgnd1 ir d8 d7 d6 d5 d4 d3 d2 d1 d0 n.c. n.c. v v v v v v v v tda8761a mbg909
1998 nov 03 5 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a limiting values in accordance with the absolute maximum rating system (iec 134). note 1. the supply voltages v cca , v ccd and v cco may have any value between - 0.3 and +7.0 v provided that the supply voltage differences d v cc are respected. handling inputs and outputs are protected against electrostatic discharges in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. thermal characteristics symbol parameter conditions min. max. unit v cca analog supply voltage note 1 - 0.3 +7.0 v v ccd digital supply voltage note 1 - 0.3 +7.0 v v cco output stages supply voltage note 1 - 0.3 +7.0 v d v cc supply voltage differences between v cca and v ccd - 1.0 +1.0 v v ccd and v cco - 1.0 +4.0 v v cca and v cco - 1.0 +4.0 v v i input voltage referenced to agnd - 0.3 +7.0 v v i(p-p) ac input voltage for switching (peak-to-peak value) referenced to dgnd - v ccd v i o output current - 10 ma t stg storage temperature - 55 +150 c t amb operating ambient temperature 0 +70 c t j junction temperature - +150 c symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 110 k/w
1998 nov 03 6 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a characteristics v cca =v 3 to v 4 = 4.75 to 5.25 v; v ccd =v 11 to v 12 and v 28 to v 27 = 4.75 to 5.25 v; v cco =v 13 to v 14 = 3.0 to 5.25 v; agnd and dgnd shorted together; t amb =0to70 c; typical values measured at v cca =v ccd = 5 v and v cco = 3.3 v; v i(p-p) = 1.8 v; c l = 15 pf and t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output stages supply voltage 3.0 3.3 5.25 v d v cc supply voltage differences between v cca and v ccd - 0.2 - +0.2 v v cca and v cco - 0.2 - +2.25 v v ccd and v cco - 0.2 - +2.25 v i cca analog supply current - 18 24 ma i ccd digital supply current - 13 18 ma i cco output stages supply current f clk = 30 mhz; ramp input - 12 ma inputs c lock input clk ( referenced to dgnd); note 1 v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 2 - v ccd v i il low-level input current v clk = 0.8 v - 10+1 m a i ih high-level input current v clk =2v - 210 m a z i input impedance f clk = 30 mhz - 2 - k w c i input capacitance - 2 - pf i nputs oe and tc ( referenced to dgnd); see table 2 v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 2 - v ccd v i il low-level input current v il = 0.8 v - 1 -- m a i ih high-level input current v ih = 2.0 v -- 1 m a v i ( analog input voltage referenced to agnd) i il low-level input current v i =v rb = 1.3 v - 17 -m a i ih high-level input current v i =v rt = 3.43 v - 35 -m a z i input impedance f i = 10 mhz - 8 - k w c i input capacitance - 5 - pf
1998 nov 03 7 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a reference voltages for the resistor ladder ; see table 1 v rb reference voltage bottom 1.2 1.3 2.45 v v rt reference voltage top 3.2 3.43 v cca - 0.8 v v diff differential reference voltage v rt - v rb 2 2.13 3.0 v i ref reference current v rt - v rb = 2.13 v - 8.7 - ma r lad resistor ladder - 245 -w tc rlad temperature coef?cient of the resistor ladder - 1860 - ppm - 456 - m w /k v osb offset voltage bottom note 2 - 160 - mv v ost offset voltage top note 2 - 160 - mv v i(p-p) analog input voltage (peak-to-peak value) note 3 1.7 1.81 2.55 v outputs d igital outputs d8 to d0 and ir ( referenced to ognd) v ol low-level output voltage i ol = 1 ma 0 - 0.5 v v oh high-level output voltage i oh = - 1ma v cco - 0.5 - v cco v i oz output current in 3-state mode 0. 5v 1998 nov 03 8 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a b andwidth (f clk =30mh z ) b analog bandwidth full-scale sine wave; note 6 - 15 - mhz 75% full-scale sine wave; note 6 - 20 - mhz small signal at mid-scale; v i = 10 lsb at code 256; note 6 - 350 - mhz t stlh analog input settling time low-to-high full-scale square wave; fig.6; note 7 - 1.5 3.0 ns t sthl analog input settling time high-to-low full-scale square wave; fig.6; note 7 - 1.5 3.0 ns h armonics (f clk =30mh z ); see figs 7 and 8 thd total harmonic distortion f i = 10 mhz -- 56 - db s ignal - to - noise ratio ; see figs 7 and 8; note 8 snr signal-to-noise ratio (full scale) without harmonics; f clk = 30 mhz; f i = 10 mhz 53 55 - db e ffective bits ; see figs 7 and 8; note 8 enob effective bits f clk = 30 mhz f i = 4.43 mhz - 8.8 - bits f i = 10 mhz - 8.2 - bits t wo - tone ; note 9 ttir two-tone intermodulation rejection f clk = 30 mhz -- 56 - db b it error rate ber bit error rate f clk = 30 mhz; f i = 10 mhz; v i = 16 lsb at code 256 - 10 - 13 - times/ sample d ifferential gain ; note 10 g diff differential gain f clk = 30 mhz; pal modulated ramp - 0.5 - % d ifferential phase ; note 10 j diff differential phase f clk = 30 mhz; pal modulated ramp - 0.3 - c symbol parameter conditions min. typ. max. unit
1998 nov 03 9 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a notes 1. in addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 0.5 ns. 2. analog input voltages producing code 0 up to and including code 511: a) v osb (voltage offset bottom) is the difference between the analog input which produces data equal to 00 and the reference voltage bottom (v rb ) at t amb =25 c. b) v ost (voltage offset top) is the difference between v rt (reference voltage top) and the analog input which produces data outputs equal to code 511 at t amb =25 c. 3. in order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 511 respectively) are connected to pins v rb and v rt via offset resistors r ob and r ot as shown in fig.3. a) the current flowing into the resistor ladder is and the full-scale input range at the converter, to cover code 0 to code 511, is b) since r l , r ob and r ot have similar behaviour with respect to process and temperature variation, the ratio will be kept reasonably constant from device to device. consequently variation of the output codes at a given input voltage depends mainly on the difference v rt - v rb and its variation with temperature and supply voltage. when several adcs are connected in parallel and fed with the same reference source, the matching between each of them is then optimized. 4. f i = 10 mhz and f clk = 30 mhz; f i = 8 mhz and f clk = 20 mhz. 5. 6. the analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. no glitches greater than 2 lsbs, neither any significant attenuation are observed in the reconstructed signal. 7. the analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square wave signal) in order to sample the signal and obtain correct output data. timing (f clk = 30 mhz; c l = 15 pf) ; see fig.4; note 11 t ds sampling delay time - 3 - ns t h output hold time 4 -- ns t d output delay time v cco = 4.75 v - 10 13 ns v cco = 3.15 v - 12 15 ns c l digital output load -- 15 pf 3-state output delay times ; see fig.5 t dzh enable high - 5.5 8.5 ns t dzl enable low - 12 15 ns t dhz disable high - 19 24 ns t dlz disable low - 12 15 ns symbol parameter conditions min. typ. max. unit i l v rt v rb C r ob r l r ot ++ ----------------------------------------- - = v i r l i l r l r ob r l r ot ++ ----------------------------------------- - == v rt ( v rb ) C 0. B 852 v ( rt v rb ) C = r l r ob r l r ot ++ ----------------------------------------- - ger v 511 v 0 C () v i(p-p) C v i(p-p) --------------------------------------------------- - 100 =
1998 nov 03 10 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a 8. effective bits are obtained via a fast fourier transform (fft) treatment taking 8 k acquisition points per equivalent fundamental period. the calculation takes into account all harmonics and noise up to half of the clock frequency (nyquist frequency). conversion to signal-to-noise ratio: s/n = enob 6.02 + 1.76 db. 9. intermodulation measured relative to either tone with analog input frequencies of 10.0 and 10.10 mhz. the two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter. 10. measurement carried out using video analyser vm700a, where the video analog signal is reconstructed through a digital-to-analog converter. 11. output data acquisition: the output data is available after the maximum delay time of t d . fig.3 explanation of note 3. handbook, halfpage r lad r ot v rt v rm v rb r ob i l r l code 511 code 0 7 6 9 mgd233
1998 nov 03 11 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a table 1 output coding and input voltage (typical values; referenced to agnd, v rb = 1.3 v, v rt = 3.43 v) table 2 mode selection step v i(p-p) ir binary output bits twos complement output bits d8 d7 d6 d5 d4 d3 d2 d1 d0 d8 d7 d6 d5 d4 d3 d2 d1 d0 u/f <1.46 0000000000100000000 0 1.46 1000000000100000000 1 . 1000000001100000001 . . ................... . . ................... 510 . 1111111110011111110 511 3.27 1111111110011111111 o/f >3.27 0111111110011111111 tc oe d8 to d0 ir x 1 high impedance high impedance 0 0 active; twos complement active 1 0 active; binary active fig.4 timing diagram. handbook, full pagewidth ds t sample n + 1 sample n clk mbg908 sample n + 2 50% 0 v v ccd 50% 0 v v cco v l data d0 to d8 t d t h cph t cpl t data n + 1 data n data n - 1 data n - 2
1998 nov 03 12 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a f oe = 100 khz. fig.5 timing diagram and test conditions of 3-state output delay time. n dbook, full pagewidth mbg907 50 % 50 % high low dzh t dhz t 50 % high low dzl t dlz t 10 % 90 % output data v ccd output data 3.3 k w 15 pf s1 v ccd tda8761a oe oe test dlz t dzl t dhz t dzh s1 ccd v ccd v dgnd dgnd t fig.6 analog input settling-time diagram. handbook, full pagewidth mgc359 50 % stlh t 2 ns code 0 code 511 i 50 % 0.5 ns 50 % 2 ns sthl t 50 % 0.5 ns clk v
1998 nov 03 13 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a fig.7 typical fast fourier transform (f clk = 30 mhz; f i = 4.43 mhz). effective bits: 8.70; thd = - 68.68 db. harmonic levels (db): 2nd = - 78.40; 3rd = - 72.08; 4th = - 75.85 db; 5th = - 76.26; 6th = - 80.23. handbook, full pagewidth 0 120 0 1.25 2.50 mbg912 40 80 6.26 3.76 5.01 7.51 8.77 10.0 f (mhz) 100 20 60 amplitude (db) fig.8 typical fast fourier transform (f clk = 30 mhz; f i = 10 mhz). effective bits: 8.25; thd = - 56.72 db. harmonic levels (db): 2nd = - 62.21; 3rd = - 58.58; 4th = - 80.29; 5th = - 71.71; 6th = - 72.04. handbook, full pagewidth 0 120 0 1.87 3.75 mbg911 40 80 9.37 5.62 7.50 11.2 13.1 15.0 f (mhz) 100 20 60 amplitude (db)
1998 nov 03 14 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a fig.9 typical ac inl (f clk = 30 mhz; f i = 10 mhz). handbook, full pagewidth 0.6 0.8 1 - 1 - 0.8 0 100 200 300 code lsb 500 400 - 0.2 0 0.2 0.4 - 0.6 - 0.4 fce166 fig.10 typical ac dnl (f clk = 30 mhz; f i = 10 mhz). handbook, full pagewidth 0.6 0.8 1 - 1 - 0.8 0 100 200 300 code lsb 500 400 - 0.2 0 0.2 0.4 - 0.6 - 0.4 fce165
1998 nov 03 15 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a internal pin configurations fig.11 cmos data and in range outputs. handbook, halfpage mgd231 v cco ognd d8 to d0 ir fig.12 analog inputs. handbook, halfpage mgc040 - 1 agnd v cca v i fig.13 oe ( tc) input. handbook, halfpage mbe557 v cco ognd oe (tc) fig.14 v rb , v rm and v rt inputs. handbook, halfpage r mgd232 v rb v rm v cca agnd v rt lad
1998 nov 03 16 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a fig.15 clk input. handbook, halfpage 1.5 v v ccd dgnd clk mbe559 - 1
1998 nov 03 17 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a application information fig.16 application diagram. the analog and digital supplies should be separated and decoupled. the external voltage regulator must be built such that a good supply voltage ripple rejection is achieved with respect to the l sb value. eventually, the reference ladder voltages can be derived from a well regulated v cca supply through a resistor bridge and a decoupled capacitor. (1) v rb , v rm and v rt are decoupled to agnd. (2) pins 15 and 16 may be connected to dgnd in order to prevent noise influence. handbook, halfpage 28 27 26 25 24 23 22 21 20 19 18 17 tda8761a dgnd1 v cco d2 d3 d4 d5 d6 d7 d8 d1 d0 v ccd2 v cca 1 2 3 4 5 6 7 8 9 10 11 12 clk agnd n.c. n.c. v rb v rm v rt mbg906 16 15 13 14 100 nf 100 nf dgnd2 ognd ir oe tc v ccd1 agnd agnd 100 nf agnd v i (1) (1) (1) (2) n.c. (2)
1998 nov 03 18 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a package outline unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 1.1 0.7 8 0 o o 0.13 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.20 mm maximum per side are not included. 1.03 0.63 sot341-1 mo-150ah 93-09-08 95-02-04 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 114 28 15 0.25 y pin 1 index 0 2.5 5 mm scale ssop28: plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 a max. 2.0
1998 nov 03 19 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all ssop packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering is not recommended for ssop packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. even with these conditions, only consider wave soldering ssop packages that have a body width of 4.4 mm, that is ssop16 (sot369-1) or ssop20 (sot266-1) . during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1998 nov 03 20 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1998 nov 03 21 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a notes
1998 nov 03 22 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a notes
1998 nov 03 23 philips semiconductors product speci?cation 9-bit analog-to-digital converter for digital video tda8761a notes
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+41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 printed in the netherlands 545104/750/03/pp24 date of release: 1998 nov 03 document order number: 9397 750 04668

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